1. Field of the Invention
This invention relates to a semiconductor memory device, specifically to an improved verify-judgment method in a write/erase mode of an electrically rewritable and non-volatile memory (EEPROM).
2. Description of the Related Art
A NAND-type flash memory is known as one of EEPROMs, which has such features as follows: unit cell area thereof is smaller than that of the NOR-type flash memory; and it is easy to make the capacity large. Therefore, it is mainly adapted to such applications as a file memory and the like.
Usually, data write of the NAND flash memory is executed by a page (for example, one page is formed of 2 kByte main column and 64 Byte redundant column) while data erase thereof is executed by a block (for example, one block is formed of 128 pages).
Since there are variations in memory cell characteristics, data write and erase are executed together with write-verify and erase-verify for verifying the write state and erase state, respectively. Further, in case an error checking and correcting system (e.g., ECC system) is prepared inside or outside the memory chip, a certain number of fails may be dealt with a “pseudo-pass” state as being defined by the ability of the ECC system.
From the above-described view point, there has already been provided a verify-judge circuit, in which a permissible fail number is settable (refer to, for example, JP-P2002-140899A).
Since the verify-judge circuit is for judging the verify result based on data stored in data latches disposed in a page sense amplifiers (i.e., page buffers), detection line thereof is basically disposed on the sense amplifier circuit area. FIG. 16 shows the schematic layout. That is, sense amplifiers PB are arranged along one side of the cell array while row decoder RowDEC is disposed on another side perpendicular to it. Detection line LSEN is disposed to cross the sense amplifier circuit area, and a fail number detection circuit is disposed at one end of the sense amplifier circuit area for detecting the level transition of the detection line LSEN to judge the fail number.
According to this configuration, the more the number of one page sense amplifiers, by which a collective read/write range is defined, the larger the parasitic resistance of the detection line LSEN or ground potential line GND crossing the sense amplifier circuit area. This will affect the precision of the verify-judgment. Specifically, in case a current comparison scheme is used for verify-judging, it becomes impossible to precisely detect the fail number (fail column number or fail bit number) because some noises are added from other lines.
For example, FIG. 17 shows a relationship between current Ifail flowing on the detection line LSEN and the fail number. Current Ifail is dispersed in relation to the fail number. Comparing the current Ifail with a reference current Iref shown in FIG. 17, it will be detected that the fail number is under a certain value.
To avoid erroneous PASS/FAIL detection, as shown in FIG. 17, the reference current Iref is usually set at the center value between adjacent two dispersed fail current values. However, if the fail current-fail number characteristic is changed due to a parasitic wiring resistance and the like, it becomes impossible to detect precisely the fail number. Especially, in case the permissible fail number is set to be large, it will often occur to erroneously detect the fail number.
In the recent flash memory, for the purpose of improving the write performance, the page length, i.e., data write unit, trends toward increasing. On the other hands, as the flash memory is miniaturized more, it becomes necessary to install an ECC system for securing data reliability. The ECC system is so formed as to embed an error correcting code in a redundant area in a page, thereby detecting and correcting an error bit(s) at a read time. As the page length is increased more, the number of redundant columns assigned to the ECC circuit is increased more, and this results in that more write-insufficient and more erase-insufficient data become permissible.
If the verify-judging circuit is not able to detect precisely the fail number, thereby erroneously detecting a to-be-detected “FAIL” state as a “PASS” state, it means that the write sequence ends with a non-correctable defect. By contrast, if the verify-judging circuit detects a to be-detected “PASS” state as a “FAIL” state, this means that the performance of the flash memory has been judged severely over the necessity, and there is a fear of shortening the life time apparently.